SiC CMOS Design-Contest

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CMOS Technology Based Sensing and Signal Processing Operable up to 600 °C

Our SiC CMOS technology, available via EUROPRACTICE, is at the forefront of innovation, offering unique performance in extremely harsh environments and enabling high temperature operation up to 600°C. Join our design contest to push the limits and make your mark in CMOS design using our advanced SiC CMOS technology for high temperature applications.

  • Competition in analog and digital CMOS circuit design
  • Exciting opportunity to show your skills and creativity
  • Winners receive free chip area on the next EUROPRACTICE run

Participate in any of these three categories

Operational Amplifier

  • Operational amplifier functional within a temperature range of 25 to 500°C
  • Voltage amplifier featuring differential input voltage signal and single-ended voltage output
  • High open-loop voltage gain and good temperature stability are essential
  • Compensation design for parameter variability (mismatch) is preferable


  • Four-channel multiplexer for analog signals
  • At least four analog inputs and one analog output required
  • Expandable to support additional channels
  • Channel selection achieved via a digital (2-bit) input
  • Enable signal required (1-bit)
  • Break-before-make design is necessary
  • Compensation design for parameter variability (mismatch) is preferable

Pulse Width Modulator

  • Pulse width modulator with an 8-bit counter
  • On-time and period must be set using 8-bit digital inputs each (duty cycle = on time / period)
  • Higher resolution with more bits is possible
  • Output is a PWM signal
  • Clock signal input for an external clock
  • Enable signal input required
  • Compensation design for parameter variability (mismatch) is preferable

Timeline for the Design Contest

Opening of Contest

opens July 1st 2024

  • Download our NDA, sign, and send it to get access to our preliminary PDK
  • Use our PDK with technology information and compact models to get familiar with the technology
  • Note that PDK will be updated for the final contest version by August 1st 2024 for the start of the contest

Start of Design Process

1st Aug 2024

  • Make sure that you have downloaded the latest PDK
  • Start designing and simulating your circuit(s) for at least one of the three categories
  • Detailed boundary conditions for participation and rules of the contest will soon be available here

Deadline for Submission

1st Nov 2024

  • Upload your design and all required files as described in the entry form

Announcement of Results

1st Dec 2024

  • Winners will be informed by e-mail and will be announced on this website and on LinkedIn

Join Us in the Pursuit of Scientific Excellence

Collaborate with Fraunhofer IISB to embark on a transformative journey at the intersection of science and technology.
Use the contact form on the right to contact Mathias Rommel, Group Manager for SiC CMOS
Circuit Design and Characterization, and together, let us push the boundaries of scientific exploration.