SiC CMOS Design-Contest

Celebrating Innovation and Excellence in the 4H-SiC-CMOS Design Contest!

We are thrilled to announce the winners of the 4H-SiC-CMOS Design Contest. A team of 3 talented students from Stanford University, USA, and Universidad Industrial de Santander, Colombia, has developed an outstanding design that we are excited to share:

Category: Operational Amplifier

"For this project, we designed a 100 dB, 20V operational amplifier (Opamp) using SiC technology. The rail-to-rail input stage supports a wide range of common-mode input voltages, while a class AB output stage ensures a high slew rate. The bias current is internally generated by a dedicated PTAT (proportional to absolute temperature) Beta-multiplier. The proposed topology employs a 3-stage of amplification to achieve high gain across a broad temperature range, from room temperature up to 500 °C."

We extend our heartfelt congratulations to the team for their outstanding work and dedication!